The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component that can be created using a fabrication process) has decreased.
As lithographic features are reduced, for example to below 40 nanometers (nm), high numerical aperture processes are needed to overcome the resolution limit. The use of a multilayer photoresist film scheme, such as a trilayer photoresist film scheme, appears to be promising in this regard. Specifically, multilayer photoresist films can provide for improvements in line edge roughness (LER) and line width roughness (LWR), among other benefits.
However, using multilayer schemes may pose challenges, especially with the decreasing technology nodes and pitch provided between features. Therefore, it is a challenge to improve the multilayer photoresist film scheme in order to improve the reliability of semiconductor devices at smaller and smaller sizes.